MOS technology integrated circuits and the low-voltage supplied portions of devices integrated with mixed-type technologies, such as logic circuits included in such devices, can suffer serious damage from electrostatic discharges (ESD) at their terminals. Malfunction or damage may also result from the application of overvoltages to their supply terminals.
With respect to electrostatic discharges, it is a recognized fact that the terminals of an integrated circuit may incidentally come in contact with electrically charged objects, both during their fabrication and their inclusion in a circuit assembly, or additionally while in operation. When this occurs, potential differences of a substantial magnitude may be established in the integrated circuit device, for example, between the gate electrodes of input transistors or the drain regions of output transistors, and the semiconductor material substrate on which the integrated circuit is formed. In the former case, when the potential difference exceeds the dielectric strength threshold of the gate insulator, the transistor is put out of use by the electrostatic discharge that develops through the insulation. In the latter case, a similar destructive effect occurs when the potential difference exceeds the reverse breakdown threshold of the drain junction. In a CMOS integrated circuit fabricated with 1.2 .mu.m technology, that is, with a minimum gate dimension of 1.2 .mu.m, the breakdown voltage is approximately 12 to 14 volts for input transistors, and approximately 12 volts for output transistors.
Several measures have been proposed for protecting the various input, output, and supply terminals from electrostatic discharges. In many cases, protection circuits utilizing bipolar side transistors have been successfully employed.
For example, a known protection circuit suitable for monolithic integration with a CMOS integrated circuit device requiring protection is disclosed in Italian Patent Application No. 26063 A/80 by the Assignee of the present invention. The protection circuit basically comprises of an NPN side transistor whose emitter and collector are doped with impurities of the N-type, similarly and simultaneously with the source and drain regions of the IGFETs of the MOS circuit to be protected, and whose unaccessible base is heavily and deeply doped by ion implantation with impurities of the P-type.
In Italian Patent Application No. 23077 A/85 by the Assignee of the present invention, an improved use of the same structure is disclosed. The improved protection circuit comprises a first and a second bipolar side transistor having their collector terminals respectively connected to the input terminal of the circuit and the gate electrodes of the IGFETs. The first and second transistors have their emitter terminals jointly connected to a ground terminal, and a diffused resistor (R') connecting the collectors of the two side transistors. The width of the first transistor base and the concentration of impurities in the bases of both side transistors are effective to keep the voltage that triggers the appearance of negative resistance in the first side transistor, and the breakdown voltage in the second side transistor, at a value below the breakdown voltage of the gate isolating oxides and below the breakdown voltage of the bipolar junctions contained in the integrated circuit. The transistor base width and concentration of impurities are also effective to keep the sustaining voltage of the first side transistor at a value above the supply voltage to the integrated circuit.
Another known protection circuit that is simple and effective in protecting against electrostatic discharges is a bipolar transistor with its base and emitter shorted together and connected between the terminal to be protected and ground. The transistor would then have a bistable current/voltage characteristic where the transistor has a high impedance, high voltage state, referred to as BVcbo in the art, and a low impedance, low voltage state, referred to as BVcer. The transistor would operate in the first state during normal operation of the circuit, and leave it unconcerned. But on the occurrence of an electrostatic discharge, the transistor would be forced to operate in the second state, thereby providing a way to ground for a discharge pulse.
However, the effectiveness of these circuits that use bipolar transistors dwindles considerably when a supply line or terminal is to be protected. In fact, BVcbo and BVcer may have statistical process variations that result in their effective values being inconsistent with the circuit operation requirements where a line or terminal is at the highest potential provided in the integrated circuit.
Moreover, voltage noise on the supply line or terminal to be protected could inadvertently turn on the bipolar transistor protection circuit and cause the supply voltage to be clamped at BVcer, a value far lower than that intended for powering the circuit. This may result not only in circuit malfunction, but also in permanent damage due to the large current flowing directly through the circuit.